查看完整版本: hex文件读取任务和应用实例(systemverilog)

hex文件读取任务和应用实例(systemverilog)

用于初始化存储器，省的再用工具进行hex->bin转换，自己改写的,出了什么问题还请各位指教

`define rom_size 16'hffff

module irom64kx8(     
input  [15:0] irom_addr,
input  irom_rd_n,
input  irom_cs_n,
output reg [7:0] irom_data_out
);

logic [7:0] rom_data[`rom_size];
logic [7:0] temp;
int i=0;
int h_mt;
initial begin
read_hex_file("../soft/main.hex",rom_data);
end
always @(*) begin
irom_data_out<=((~irom_rd_n) && (~irom_cs_n))? rom_data[irom_addr]:8'bZ;
end

[color=red][b]task read_hex_file(input string file_name , output [7:0] rom_data[`rom_size]);
logic [7:0]  column;
logic [15:0] address;
logic [7:0] len;
logic [7:0] dat;
logic [7:0] check_sum;
int i,fd,code;
//initial all data with zero
foreach(rom_data[i][/b][/color][i][color=red][b])
rom_data[i][/b][/color][i][color=red][b]=0;[/b][/color][/i][/i]
[i][i][color=red][b]
fd=$fopen(file_name,"r");
if(fd==0) begin
  $display("hex file not found,please check file path and file name!");
  $stop;            // stop when no such file
end
while(~$feof(fd)) begin
    //find ":" at the beginning of a record
while(1) begin
  if($feof(fd))begin
   $fclose(fd);
   return;
  end
  
   column=$fgetc(fd);
  if(column==":") break;    // every line begin with ":" int the IntelHex form
end
   
  
   code=$fscanf(fd,"%2x",len);
   if(len==0) return;      // stop when no data
  
   check_sum=len;
   code=$fscanf(fd,"%4x",address);
   check_sum=check_sum+address;
   check_sum=check_sum+(address>>8);  // unsigned check_sum
   code=$fscanf(fd,"%2x",dat);     // data type
   check_sum=check_sum+dat;
  
  
   for(i=0;i<len;i=i+1) begin
     code=$fscanf(fd,"%2x",dat);
     check_sum=check_sum+dat;
     rom_data[address]=dat;     // rom_data read data from file
     //$display("rom_data[%6d]=%2h",address,dat);
     address=address+1;
   end
  
   code=$fscanf(fd,"%2x",dat);   // check data
   check_sum=check_sum+dat;
  
   if(check_sum!=0) begin
     $display("hex file error:checkcheck_sum is not zero!");
     $stop;
   end
end
endtask:read_hex_file[/b]
[/color]
endmodule[/i][/i]

[[i] 本帖最后由 pengyoust 于 2008-7-11 08:56 编辑 [/i]]

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